1. Field of the Invention
This invention relates to emitter coupled logic (ECL) and in particular relates to an emitter coupled logic gate having enhanced speed characteristics.
Emitter coupled logic gates are among the fastest types of digital circuit gates. However, ECL gates have not been able to capitalize on the full speed potential of ECL in inverter gates. Moreover, ECL gates do not handle capacitive loads particularly well. What is needed is a new type of logic circuit which takes better advantage of the potential speed of bipolar technology.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a conventional ECL primitive inverter gate 10 with emitter follower output. The primitive gate 10 comprises a first input transistor Q.sub.A, a second input transistor Q.sub.B a reference transistor Q.sub.R, a current source transistor Q.sub.CS, a first load transistor Q.sub.L1, and a second load transistor Q.sub.L2. The inverter gate 10 operates between an input A and an input B to produce at an output at node 1 between the emitter of transistor Q.sub.L1 and the collector of transistor Q.sub.L2 an output A+B. The emitters of transistors Q.sub.A, Q.sub.B and Q.sub.R are coupled at a common node 3 to the collector of current source transistor Q.sub.CS. A current source bias voltage V.sub.CS is maintained at the base of transistors Q.sub.CS and Q.sub.L2. The load of transistor Q.sub.CS is through the emitter at a resistor R.sub.CS to the lowest reference voltage, herein a ground voltage. The load of transistor Q.sub.L2 is through a resistor R.sub.L in the emitter-to-ground circuit thereof. The collectors of transistors Q.sub.A and Q.sub.B are coupled in common to a node 2 and to the base of transistor Q.sub.L1. A collector load resistor R.sub.CL is coupled between the source voltage reference V.sub.CC and node 2. The collector of transistor Q.sub.L1 is connected to the V.sub.CC voltage. The collector of transistor Q.sub.R is connected to the V.sub.CC voltage. Finally, a reference voltage V.sub.BB is provided to the base of transistor Q.sub.R. Transistors Q.sub.L1 and Q.sub.L2 form the emitter follower circuit for the voltage on node 2.
Referring to FIG. 2, there is shown a conventional current mode logic (CML) primitive inverter gate 12. Current mode logic is similar to emitter coupled logic except that there is no emitter follower circuitry. One paper describing CML logic is "A 1500 Gate, Random Logic Large Scale Integrated (LSI) Masterslice", R. J. Blumberg and S. Brenner, IEEE Journal of Solid State Circuits, Volume SC-14 No. 5, page 818 (October 1979). In both of the circuits of FIGS. 1 and 2, there is an emitter dynamic resistance and a diffusion capacitance associated with the reference transistor Q.sub.R. The emitter dynamic resistance of Q.sub.R and the diffusion capacitance of Q.sub.R are in parallel and define an impedance effectively in series with the emitter of the input transistors Q.sub.A and Q.sub.B.